Field of the Invention
The present invention generally relates to the compression of page table entries (PTEs) as they are read from a memory and stored into a translation lookaside buffer (TLB).
Description of the Related Art
Modern graphics processing units (GPU), central processing units (CPU), and operating systems (OS) manage memory using virtual addressing. Application programs and the engines within the GPU and CPU use virtual addresses. The operating system and/or driver allocate physical memory for ranges of virtual addresses and specify the mapping between virtual and physical addresses using page tables. A page table entry (PTE) describes the mapping for a range of virtual addresses to a range of physical addresses. The translation from virtual addresses to physical addresses is performed by a memory management unit (MMU) that may be configured to cache PTEs in order to improve the performance by eliminating the need to read PTEs for every translation.
The efficiency of caching the PTEs improves as the number of PTEs capable of being stored in the cache increases. This may be accomplished through physically increasing the size or storage capacity of the cache. However, such physical changes are often costly and undesirable.
Accordingly, what is needed in the art is a system and method for increasing the storage capacity of a cache without modifying the physical attributes of the cache.